spt5310 12-bit, 250 mwps ecl d/a converter signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 applications ? fast frequency hopping spread spectrum radios ? direct sequence spread spectrum radios ? microwave and satellite modems ? test & measurement instrumentation ? military applications features ? 12-bit, 250 mwps digital-to-analog converter ? ecl compatibility ? low glitch energy: 15 pv-s ? low power: 600 mw ? 40 mhz multiplying bandwidth ? master-slave latches ? industrial temperature range r set control amp in (msb) latch enable digital inputs d1 through d12 ref in i out i out decoders and drivers latches (lsb) - control amp + control amp out internal voltage reference ref out switch network block diagram general description the spt5310 is a 12-bit, 250 mwps digital-to-analog con- verter designed for direct digital synthesis, high resolution imaging and arbitrary waveform generation applications. the spt5310 is an ecl-compatible device. it features a low glitch impulse energy of 15 pv-s that results in excellent spurious free dynamic range characteristics. the spt5310 is available in 28-lead plastic dips and 28-lead plccs in the industrial temperature range (-40 to +85 c).
spt 2 4/1/97 spt5310 absolute maximum rating (beyond which damage may occur) 1 supply voltages negative supply voltage (v ee ) ................................ -7 v a/d ground voltage differential .............................. 0.5 v input voltages digital input voltage (d1-d12, latch enable) ................. ....................................................................... 0 v to v ee control amp input voltage range ................. 0 v to -4 v reference input voltage range (v ref ) ..... -3.7 v to v ee output currents internal reference output current ....................... 500 m a control amplifier output current ........................ 2.5 ma temperature operating temperature ............................. -40 to + 85 c junction temperature ........................................ + 150 c lead, soldering (10 seconds) ............................ + 300 c storage .................................................... -65 to + 150 c note : 1. operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical applications. 1 gain is measured as a ratio of the full-scale current to i set . the ratio is nominally 128. 2 measured as voltage at mid-scale transition to 0.024%; r l =50 w . 3 measured from the rising edge of latch enable to where the output signal has left a 1 lsb error band. 4 glitch is measured as the largest single transient. 5 calculated using i fs =128 x control amp in r set 6 sfdr is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. dc performance resolution 12 bits differential linearity i 1.0 1.25 lsb differential linearity max at full temp. vi 2.0 lsb integral linearity best fit i 1.0 1.5 lsb integral linearity max at full temp. vi 2.0 lsb output capacitance +25 c10pf gain error 1 +25 c i 1.0 5.0 % fs full temp. vi 8.0 % fs gain error tempco full temp. v 150 ppm/ c zero-scale offset error +25 c i 0.5 2.5 m a full temp. vi 5.0 m a offset drift coefficient full temp. v 0.01 m a/ c output compliance voltage +25 c iv -1.2 +2.0 v equivalent output resistance +25 c iv 0.8 1.0 1.2 k w dynamic performance conversion rate +25 c iv 250 mwps settling time t st 2 +25 c v 13 ns output propagation delay t d 3 +25 cv 1 ns glitch energy 4 +25 c v 15 pv-s full scale output current 5 +25 c v 20.48 ma electrical specifications t a = t min - t max , v ee = -5.2 v, r set = 7.5 k w , control amp in = ref out, v out = 0 v, unless otherwise specified. test test spt5310 parameters conditions level min typ max units
spt 3 4/1/97 spt5310 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/ max specifications are guaranteed. the test level column indicates the specific device test- ing actually performed during production and quality assurance inspection. any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. electrical specifications t a = t min - t max , v ee = -5.2 v, r set = 7.5 k w , control amp in = ref out, v out = 0 v, unless otherwise specified. test test spt5310 parameters conditions level min typ max units dyanmic performance spurious-free dynamic range 6 +25 c 5.055 mhz; 20 mwps 2 mhz span v 63 dbc 10.055 mhz; 40 mwps 2 mhz span v 58 dbc 20.055 mhz; 80 mwps 2 mhz span v 56 dbc 40.055 mhz; 160 mwps 2 mhz span v 54 dbc 60.055 mhz; 240 mwps 2 mhz span v 46 dbc rise time / fall time r l = 50 w v2ns power supply requirements negative supply voltage iv -5.46 -5.2 -4.94 v negative supply current (-5.2 v) +25 c i 115 140 ma full temp vi 148 ma nominal power dissipation v 600 mw power supply rejection ratio 5% of v ee i 30 100 m a/v external ref, +25 c voltage input and control reference input impedance +25 cv 3k w ref. multiplying bandwidth +25 c v 40 mhz internal reference voltage vi -1.15 -1.20 -1.25 v internal reference voltage drift v 50 ppm/ c amplifier input impedance +25 cv 3m w amplifier input bandwidth +25 c v 1 mhz digital inputs logic 1 voltage full temp. vi -1.0 -0.8 v logic 0 voltage full temp. vi -1.7 -1.5 v logic 1 current full temp. vi 20 m a logic 0 current full temp. vi 10 m a input capacitance +25 cv 3pf input setup time - t s +25 civ32ns input setup time - t s full temp. iv 3.5 ns input hold time - t h +25 c iv 0.5 0 ns input hold time - t h full temp. iv 0.5 ns latch pulse width - t pwl , t pwh +25 c iv 4.0 3.3 ns
spt 4 4/1/97 spt5310 theory of operation the spt5310 uses a segmented architecture incorporating most significant bit (msb) decoding. the four msbs (d1-d4) are decoded to thermometer code lines to drive 15 discrete current sinks. for the eight least significant bits (lsbs), d5 and d6 are binary weighted and d7-d12 are applied to the r-2r network. the 12-bit decoded data is input to internal master/slave latches. the latched data is input to the switch- ing network and is presented on the output pins as comple- mentary current outputs. typical interface circuit the spt5310 requires few external components to achieve the stated operation and performance. figure 2 shows the typical interface requirements when using the spt5310 in normal circuit operation. the following sections provide de- scriptions of the pin functions and outlines critical perfor- mance criteria to consider for achieving optimal device per- formance. power supplies and grounding the spt5310 requires the use of a single -5.2 v supply. all supplies should be treated as analog supply sources. this means the ground returns of the device should be connected to the analog ground plane. all supply pins should be by- passed with .01 m f and 10 m f decoupling capacitors as close to the device as possible. the two grounds available on the spt5310 are dgnd and agnd. these grounds are not tied together internal to the device. the use of ground planes is recommended to achieve the best performance of the spt5310. all ground, reference and analog output pins should be tied to directly to the dac ground plane. the dac and system ground planes should be separate from each other and only connected at a single point through a ferrite bead to reduce ground noise pickup. digital inputs and timing the spt5310 uses single-ended, 10k ecl-compatible in- puts for data inputs d1-d12 and latch enable. it also em- ploys master/slave latches to simplify digital interface timing requirements and reduce glitch energy by synchronizing the current switches. this is an improvement over the ad5310, which typically requires external latches for digital input synchronization. referring to figure 1, data is latched into the dac on the rising edge of the latch enable clock with the associated setup and hold times. the output transition occurs after a typical 1 ns propagation delay and settles to within 1 lsb in typically 13 ns. because of the spt5310s rising edge-triggering, no timing changes are required when replacing an ad5310 operating in nontransparent mode. voltage reference when using the internal reference, ref out should be con- nected to control amp in and decoupled with a 0.1 m f capacitor. control amp out should be connected to ref in and decoupled to the analog supply. (see figure 2.) full-scale output current is determined by control amp in and r set using the following formula: i out (fs) = (control amp in / r set ) x 128 (current out is a constant 128 factor of the reference current) the internal reference is typically -1.20 v with a tolerance of 0.05 v and a typical drift of 50 ppm/ c. if greater accuracy or temperature stability is required, an external reference can be utilized. outputs the output of the spt5310 is comprised of complementary current sinks, i out and i out . the output current levels at either i out or i out are based upon the digital input code. the sum of the two is always equal to the full-scale output current minus one lsb. by terminating the output current through a resistive load to ground, an associated voltage develops. the effective resis- tive load (r eff ) is the output resistance of the device (r out ) in parallel with the resistive load (r l ). the voltage which devel- ops can be determined using the following formulas: control amp out = -1.2 v, and r set = 7.5 k w i out (fs) = (-1.2 v / 7.5 k w ) x 128 = -20.48 ma r l = 51 w r out = 1.0 k w r eff = 51 w || 1.0 k w = 48.52 w v out = r eff x i out (fs) = 48.52 w x -20.48 ma = -0.994 v the resistive load of the spt5310 can be modified to incor- porate a wide variety of signal levels. however, optimal device performance is achieved when the outputs are equiva- lently loaded.
spt 5 4/1/97 spt5310 figure 1 - timing diagram -1.3 v latch enable t pwl t h t s t pwh out + out - 1/2 lsb t st 1 lsb -1.3 v t d data inputs figure 2 - typical interface circuit 15,25 12,21 0.1 f 0.1 f 0.001 f 0.001 f 23 r l r l 14 16 24 r set 19 20 18 17 20 w av ee i out i out r set control amp in ref out control amp out ref in d1 (msb) d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 (lsb) le 28 1 2 3 4 5 6 7 8 9 10 11 26 dgnd agnd ref gnd system gnd ecl logic drivers 0.1 f -5.2 v v out digital inputs clock input spt5310 27 13 22 dv ee n/c 10 f 0.1 f
spt 6 4/1/97 spt5310 package outlines 28l plastic dip a b c d e 1 28 j k f g h i inches millimeters symbol min max min max a 0.200 5.08 b 0.120 0.135 3.05 3.43 c 0.020 0.51 d 0.100 2.54 e 0.067 1.70 f 0.013 0.33 g 0.170 0.180 4.32 4.57 h 0.622 15.80 i 0.555 14.10 j 1.460 37.08 k 0.085 2.16
spt 7 4/1/97 spt5310 package outlines 28l plcc a b pin 1 c d e f g h top view pin 1 bottom view i inches millimeters symbol min max min max a 0.450 0.456 11.43 11.58 b 0.485 0.495 12.32 12.57 c 45 45 d 0.165 0.175 4.19 4.45 e 0.010 0.25 f 0.022 typ .56 typ g 0.18 typ 4.57 typ h 0.05 typ 1.27 typ i 0.039 0.430 0.99 10.92
spt 8 4/1/97 spt5310 pin assignments pin functions name function out+ analog current output out- complementary analog current output d 1 -d 12 digital input bits (d 12 is the lsb) latch enable latch control line ref in voltage reference input ref out internal voltage reference output normally connected to control amp in ref gnd ground return for internal voltage reference and amplifier control amp in normally connected to ref out if not connected to external reference control amp out output of internal control amplifier normally connected to ref in r set 1 connection for external resistance reference when using internal amplifier nominally 7.5 k w analog return analog return ground analog v ee analog negative supply (-5.2 v) digital v ee digital negative supply (-5.2 v) dgnd digital ground return n/c not connected 1 full-scale current out=128 (control amp in/r set ) aaaaaaaaaa aaaaaaaaaa 25 24 23 22 21 20 19 5 6 7 8 9 10 11 18 17 16 15 14 13 12 26 27 28 1 2 3 4 analog v ee r set n/c ref gnd digital v ee ref out control amp in d6 d7 d8 d9 d10 d11 (lsb) d12 latch enable dgnd (msb) d1 d2 d3 d4 d5 control amp out ref in analog v ee i out analog return digital v ee i out plcc ordering information part number dnl/inl package spt5310 sin 1.25/ 1.5 28l pdip spt5310 sip 1.25/ 1.5 28l plcc signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is hereby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. analog v ee r set n/c ref gnd digital v ee ref out control amp out latch enable dgnd d1 (msb) control amp in ref in analog v ee i out 24 23 22 21 20 19 18 17 16 15 28 27 26 25 5 6 7 8 9 10 11 12 13 14 1 2 3 4 digital v ee d6 d7 d8 d9 d10 d11 (lsb) d12 d2 d3 d4 d5 analog return i out pdip
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